UPD7220 Video Card (Revision 2)

The uPD7220 Video Card revision 2 is a video card with 128KB of VRAM using the uPD7220 GDC or its variants. It operates at a maximum clock speed of 32Mhz. The card is based on the original uPD7220 card I (Dylan Brophy) made, which had half the VRAM and generally was far simpler. This card solves several issues with the older card, at the cost of greater size and complexity.

Detailed Specifications

• 16-color VGA output
• 128KB of RAM
  • 4 RAM chips, 32KB each, 25ns access and write time
  • 16 bit bus (8 bits per chip, two chips per byte)
  • 4 color bits per pixel, 4 pixels per word in RAM
    • Maximum 262144 pixels (hardware double buffering disabled)
      • Suggested resolutions: 544x480, 640x408
    • Maximum 131072 pixels (hardware double buffering enabled)
      • Suggested resolutions: 448x288, 400x300
• uPD7220 at up to 24Mhz, Z7220 at up to 32Mhz
• uPD7220 wide mode supported
  • Allows higher pixel clock frequencies, for higher resolutions and lower visible display times
  • Accesses two VRAM words per uPD7220 clock cycle
• Direct access to VRAM is provided to the host CPU

Video Modes

It is assumed that the reader is familiar with VGA display timings. If not, then it is recommended to study it, or to use the video timing calculator and to leave the card in wide mode.

The uPD7220 was invented before the VGA standard, and due to this, was not designed to output a VGA signal. Since VGA was designed to drive CRT monitors, as was the uPD7220, it turns out that they are fairly compatible.

Card Specific Details: Wide Mode

This card can reach quite high clock speeds for the uPD7220, and to maintain this high speed for such slow chips, wide mode is used. This allows twice as many pixels to be output per uPD7220 clock cycle. This can be used either to increase the maximum resolution, or to reduce the display time. Reducing the display time gives the uPD7220 and host processor more time to draw to the screen. On the other hand, due to the high speeds used in wide mode, there is also typically more data that must be written to the display per frame, thus putting more pressure on the host processor. The balance in display characteristics depends on the application.

Due to wide mode support, the card's clock is 4x the uPD7220's clock. When doing calculations for video, this must be kept in mind. If wide mode is disabled, then the pixel clock is only half the card's clock. If the video timing math does not account for this, then the video signal timing will be incorrect.

Communication with the Host Processor

The hardware connection uses a fairly simple 8-bit parallel bus for data exchange. Once connected, the software can read from and write to several registers and addresses on the card to control it.

Hardware Protocol

Here is a pinout of the card:

Card Pinout

Pin	Name	Description
1	A0	Address pin 0 (LSB)
2	A1	Address pin 1
3	A2	Address pin 2 (MSB)
4	NC	No connection: this is the key pin and should be blocked
5	GND	Ground connection
6	D0	Data pin 0 (LSB)
7	D1	Data pin 1
8	D2	Data pin 2
9	D3	Data pin 3
10	D4	Data pin 4
11	D5	Data pin 5
12	D6	Data pin 6
13	D7	Data pin 7 (MSB)
14	SEL	Select pin (active low input) - selects the card for communication
15	5v	+5V rail to power the card
16	RD	Read enable pin (active low input)
17	WR	Write enable pin (active low input)
18	WAIT	Wait indication (active low output)

When trying to access VRAM, if the VRAM is being used by the card, then WAIT will be pulled low to tell the CPU not to end the current operation until after the WAIT pin goes high again. After WAIT goes high, wait at least 31.25ns for the read/write operation to complete before releasing any control lines or changing any data/address lines. Never read data while WAIT is low, and wait 31.25ns after WAIT goes high before reading the data to the CPU. WAIT only becomes low when trying to read from or write to VRAM; otherwise WAIT is always high.

Each access cycle should last at least 31.25ns, and SEL should be de-asserted between cycles. Any conventional processor like Z80, 8086, 6502, etc, should have no issue with WAIT or access cycles below an operating frequency of 32Mhz, regardless of the speed of the card. There may be exceptions to this, but there are no known exceptions.

Software Protocol

Card Registers

Register	Purpose
0	uPD7220 command register (uPD7220 A0 = 0)
1	uPD7220 parameter register (uPD7220 A0 = 1)
2	Card configuration register (write only)
3	Direct VRAM access (accessing this may cause WAIT to go low)
4	VRAM Address bits 0-7 (write only)
5	Reserved - for now same as register 4
6	VRAM Address bits 8-15 (write only)
7	Reserved - for now same as register 6

For this card, a driver should first configure register 2 for the selected video mode and card interface configuration. This register has various bits to tell the card what to do:

Configuration Register Bits

Bit	Purpose
0	Enables automatic counting of the VRAM address registers if set. If reset, then the VRAM address registers do not change when VRAM is written. More on this later.
1	Setting this bit enables the card's wide mode circutry. When reset, one pixel will be output every other clock cycle. This should match the setting on the uPD7220 IC.
2	Enables automatic double buffering. When set, draws to VRAM from the host CPU or the uPD7220 will happen on the opposite buffer as the one displaying. Setting this halfs the available VRAM for displaying.
3	Reserved
4	Reserved
5	Reserved
6	Reserved
7	Controls which buffer is displaying. Changing this bit will swap the currently displaying buffer. Only works in automatic double buffer mode.

It is recommended to keep track of what buffer is currently displaying, and perhaps this entire configuration register, so that the selected buffer can be switched. This register is important for controlling how the CPU accesses VRAM, how smooth the display is, and the way the image data is displayed.